This invention relates to an image processing technology and, more particularly, to a method for varying an initial value in a pseudo-gray scale modification.
A liquid crystal display panel and a plasma display panel are examples of a thin video image producing apparatus. In the following description, term xe2x80x9cdisplay panelxe2x80x9d is used for the thin video image producing apparatus. Pieces of video data information are usually supplied to the display panel through a digital signal. The gradation of image produced on the display panel is dependent on the bits of the digital video data signal. When a piece of video data information is represented by six bits, the panel display is able to produce 64 gray levels. On the other hand, if the digital video signal contains eight bits representing a piece of video data information, the gradation range is expanded to 256 gray levels. The gradation has been changed from 6-bit gradation to 8-bit gradation.
Digital chrominance signals are assumed to carry a piece of video data information representative of a full color image. The piece of video data information is broken down into three sub-pieces of video data information representative of a sub-image colored in red, a sub-image colored in green and a sub-image colored in green, and the chrominance signals are respectively assigned to the three sub-pieces of video data information. In the following description, xe2x80x9cRxe2x80x9d, xe2x80x9cGxe2x80x9d and xe2x80x9cBxe2x80x9d stand for red, green and blue, respectively. When the gradation is changed from 6 bits to 8 bits, each of the chrominance signals requires two additional bits, and an image data processing circuit is enlarged.
A display panel is assumed to have the resolution xe2x80x9cSXGAxe2x80x9d, i.e., 1280 lines xc3x971024 lines. In order to produce a full color image on the display panel from a piece of data information, the display panel requires two ports {(RA, GA, BA), (RB, GB, BB)}, and the piece of image data information is supplied through the two ports to a controller. The output signals of the controller are reduced in frequency, and arc supplied through four ports to a driver. The controller and the driver are in the form of semiconductor integrated circuit device, and are mounted on a circuit board. Various signal lines are printed on the circuit board, and the output signals are supplied from the controller through the signal lines to the driver. The number of signal lines is calculated as 8 bits xc3x973 colors xc3x974 ports, and is 96 lines. If each of the chrominance signals includes 6 bits representative of the sub-piece of video data information, only 72 signal lines propagate the output signals. Thus, the increase of gray levels results in the enlargement of the circuit board. Moreover, the driver circuit copes with the increase of the gray levels, and is also enlarged. This results in increase of the production cost.
As described hereinbefore, the enhancement of gradation results in the enlargement of the video data processing circuit. If the video data processing circuit for the 6-bit gradation is available for the video image represented by the 8-bit video signal, the production cost is restricted. For this reason, a pseudo-gray scale modification technique such as the dither technique or the frame rate controlling technique is employed in the video data processing circuit.
One of the pseudo-gray scale modification techniques is constructed on the basis of the error diffusion, and an example is disclosed in Japanese Patent Publication of Unexamined Application No. 9-90902. The Japanese Patent Publication of Unexamined Application teaches that the error diffusion is carried out in the direction of line and that the initial value is varied at every line and every frame. The prior art pseudo-gray scale modification is hereinbelow described in detail.
FIG. 1 shows a typical example of the error diffusion circuit. The prior art error diffusion circuit has two ports (not shown), and 8-bit video data signals RA, GA, BA and RB, GB, BB are sequentially input to the associated ports. Each of the 8-bit video data signals is separated into six high-order bits and two low-order bits. The six high-order bits are directly supplied to an input port xe2x80x9caxe2x80x9d of an adder 107, and the two low-order bits are supplied through an adder 106 to the other input port xe2x80x9cbxe2x80x9d of the adder 107. The two low-order bits are supplied to an input port xe2x80x9ccxe2x80x9d of the adder 106, and a carry bit is supplied from a carry port xe2x80x9cCRYxe2x80x9d of the adder 106 to the input port xe2x80x9cbxe2x80x9d of the adder 107, and the adder 107 outputs 6-bit video data signals RA/GA/BA and RB/GB/BB.
An initial value generator 101 and a flip-flop circuit 103 are connected in parallel to two input ports xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d of a selector 102. The initial value generator 101 supplies 2-bit signal representative of an initial value to the input port xe2x80x9c1xe2x80x9d of the selector 102, and the flip-flop circuit 103 supplies the previous sum xe2x80x9cc+dxe2x80x9d to the input port xe2x80x9c0xe2x80x9d of the selector 102. The selector 102 is responsive to a control signal 105 so as to selectively connect the input ports xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d to the output port xe2x80x9cYxe2x80x9d. The output port xe2x80x9cYxe2x80x9d of the selector 102 is connected to the other input port xe2x80x9cdxe2x80x9d of the adder 106. The adder 106 adds the value at the input port xe2x80x9cdxe2x80x9d to the value at the input port xe2x80x9ccxe2x80x9d, and produces the sum xe2x80x9cc+dxe2x80x9d and the carry. The sum xe2x80x9cc+dxe2x80x9d is supplied from the output port xe2x80x9cc+dxe2x80x9d to an input port xe2x80x9cDxe2x80x9d of the flip-flop circuit 103, and the carry is supplied from the carry port xe2x80x9cCRYxe2x80x9d to the input port xe2x80x9cbxe2x80x9d of the adder 107. An internal clock signal 104 is supplied to the clock node xe2x80x9cCKxe2x80x9d of the flip-flop circuit 103, and the flip-flop circuit 103 latches the sum xe2x80x9cc+dxe2x80x9d in response to the internal clock signal 104.
When the first video data signal RA1, GA1, BA1, RB1, GB1 or BB1 of each frame is supplied through the port, the control signal 105 instructs the selector 102 to connect the initial value generator 101 to the input port xe2x80x9cdxe2x80x9d of the adder 106. The initial value is transferred through the selector 102 to the input port xe2x80x9cdxe2x80x9d of the adder 106. The initial value is added to the value represented by the two low-order bits of the first video data signal RA1/GA1/BA1/RB1/GB1/BB1. Then, the sum xe2x80x9cc+dxe2x80x9d is produced. The sum xe2x80x9cc+dxe2x80x9d is representative of an error. If the carry takes place, the carry bit is supplied from the adder 106 to the input port xe2x80x9cbxe2x80x9d of the adder 107, and is added to the six high-order bits.
The control signal 105 instructs the selector 102 to change the input port from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d. When the next internal clock signal is changed to the active level, the sum xe2x80x9cc+dxe2x80x9d is latched by the flip-flop circuit 103. The sum xe2x80x9cc+dxe2x80x9d is transferred through the selector 102 to the input port xe2x80x9cdxe2x80x9d, and is added to the two low-order bits of the second video data signal of the same frame. The control signal 105 keeps the signal propagation path from the input port xe2x80x9c0xe2x80x9d to the output port xe2x80x9cYxe2x80x9d in the selector 102 until the last video data signal.
When the first video data signal of the next frame is supplied to the port, the control signal 105 instructs the selector 102 to connect the input port xe2x80x9c1xe2x80x9d to the output port xe2x80x9cYxe2x80x9d. The initial value generator 101 supplies an initial value through the selector 102 to the input port xe2x80x9cdxe2x80x9d of the adder 106. However, the initial value is not fixed. When the line or the frame is changed, the initial value generator 101 changes the initial value.
In the prior art error diffusion circuit disclosed in Japanese Patent Publication of Unexamined Application No. 9-90902, three low-order bits are added to the previous sum, i.e., the error, and the error is circulated. The initial value generator changes the initial value as shown in FIG. 2. Eight lines form a line group, and the initial value is changed in every line group of each odd frame as xe2x80x9c7xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c4xe2x80x9d, xe2x80x9c3xe2x80x9d, xe2x80x9c5xe2x80x9d, xe2x80x9c6xe2x80x9d and xe2x80x9c0xe2x80x9d. On the other hand, the initial value generator changes the initial value in every line group of each even frame as xe2x80x9c3xe2x80x9d, xe2x80x9c5xe2x80x9d, xe2x80x9c6xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c7xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d and xe2x80x9c4xe2x80x9d. Thus, the initial value is changed between the odd frames and the even frames as well as among the lines. If the three low-order bits of each video data signal arc (0, 0, 1), the error is diffused in the direction of lines, and the prior art video data processing circuit produces an image on a display panel as shown in FIG. 3. In FIG. 3, the carry takes place at the pixels indicated by hatching lines. If the hatching lines fall from the left side toward the right side, the pixels belong to the odd frames. On the other hand, if the hatching lines fall from the right side toward the left side, the pixels belong to the even frames. The carry does not take place at the pixels without any hatching line.
The first problem inherent in the prior art video data processing circuit in unintentional stripe patter is produced on the display panel. The 8-bit video data signal with three low-order bits (0, 0, 1) is assumed to correspond a certain gray level of the 6-bit gradation. If the carry takes place in the adder 106, the adder 107 produces the 6-bit video data signal representative of a gray level higher than the certain gray level. As shown in FIG. 3, while the display panel is producing an ode frame, the carry takes place in the pixels indicated by the hatching lines falling from the left side toward the right side, and the bright pixels are obliquely arranged on the display panel like stripes. When the display panel changes the odd frame to the even frame, the carry takes place in the pixels indicated by the hatching lines falling from the right side toward the left side, and the bright pixels are also obliquely arranged like stripes. The prior art error diffusing circuit moves the bright pixels on the display panel between the odd frames and the even frames, and the stripe pattern is unintentionally produced on the display panel. The unintentional stripe pattern is due to the initial value only changed between the odd frames and the even frames.
Another problem inherent in the prior art error diffusing circuit is undesirable burning in a liquid crystal display panel. In case where the prior art error diffusing circuit supplies the 6-bit video data signals to a liquid crystal display panel, the polarity is alternated between the frames for driving the liquid crystal pixels. However, the initial values shown in FIG. 2 does not allow the prior art error diffusing circuit to alternate the polarity, because the initial value is differently changed between the odd frames and the even frames.
The Japanese Patent Publication of Unexamined Application teaches only the pattern of initial values shown in FIG. 2.
It is therefore an important object of the present invention to provide a method through which an initial value is varied for preventing a display panel from unintentional pattern and burning.
To accomplish the object, the present invention proposes to vary an initial value depending upon the combination of a frame number, a line number and a sort of input video data signals.
In accordance with one aspect of the present invention, there is provided a gray scale modifying circuit for producing a series of frames each having plural lines on a screen of an image producing apparatus comprising an input port supplied with input video data signals grouped into plural sorts, each of the input video data signals having a first predetermined number of bits representative of a piece of image to be produced in one of the frames of the series, an output port outputting output video data signals corresponding to the input video data signals, respectively, each of the output video data signals having a second predetermined number of bits representative of the piece of image, a signal converter connected between the input port and the output port, and producing the output video data signals from the input video data signals and a control data signal representative of a piece of control data information, and a control signal generator producing the control data signal used in a gray scale modification from the input video data signals belonging to a group of the sorts selected from the plural sorts to the corresponding output video data signals, and varying the piece of control data information depending upon the combination of a first number assigned to each of the frames, a second number assigned to each of the lines and the sort selected from the group of sorts and assigned to one of the input video data signals to be converted.
In accordance with another aspect of the present invention, there is provided a gray modification circuit for producing a series of frames each having plural lines on a display panel, the series of frames are divided into plural frame groups each having a first number of frames respectively assigned frame numbers, the plural lines are divided into plural line groups each having a second number of lines respectively assigned line numbers, and the gray modification circuit comprises an input port supplied with first input video data signals to last input data signals for each line, each of the first to last input video data signals having a first predetermined number of bits representative of one of the gray levels of a first gradation, the first input video data signals being grouped in color given to pieces of an image on the each line, an output port outputting first output video data signals to last output data signals for the each line, each of the first to last output data signals having a second predetermined number of bits representative of one of the gray levels of a second gradation different from the first gradation, an initial value generator producing a first control signal representative of an initial value variable depending upon the combination of the color, the frame number and the line number for each of the first input video data signals and a gray scale converter having input ports connected to the input port and the initial value generator and an output port connected to the output port and producing the first output video data signals from the first input video data signals and the first control signal and the last output video data signals from the last input video data signals and a second control signal internally produced therein.